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DS26528DK Octal T1/E1/J1 Transceiver Design Kit Daughter Card
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26528DK is an easy-to-use evaluation board for the DS26528 octal T1/E1/J1 single-chip transceiver (SCT). The DS26528DK is intended to be used as a daughter card with either the DK2000 or the DK101 (included) motherboards. The board comes complete with a DS26528 SCT, transformers, termination resistors, configuration switches, network connectors, and motherboard connectors. The DK101/DK2000 motherboard and Dallas' ChipView software give point-and-click access to configuration and status registers from a Windowsa-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status, as well as multiple clock and signal routing configurations. Each DS26528DK is shipped with a free DK101 motherboard. For complex applications, the DK2000 high-performance demo kit motherboard can be purchased separately.
Windows is a registered trademark of Microsoft Corp.
FEATURES

Demonstrates Key Functions of DS26528 T1/E1/J1 SCT Includes DS26528 SCT, Transformers, BNC and RJ48 Network Connectors, and Termination Passives BNC Connections for 75W E1 RJ48 Connectors for 120W E1 and 100W T1 Compatible with DK101 and DK2000 Demo Kit Motherboards DK101/DK2000 and ChipView Software Provide Point-and-Click Access to the DS21354 Register Set Software-Controlled (Register Mapped) Configuration Switches to Facilitate Clock and Signal Routing All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-Of-Signal and Interrupt Status as well as Indications for Multiple Clock and Signal Routing Configurations Easy-to-Read Silk Screen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs
DESIGN KIT CONTENTS
DS26528DK Daughter Card DK101 Low-Cost Motherboard CD_ROM Including: ChipView Software DS26528DK Data Sheet DK101 Data Sheet DS26528 Data Sheet DS26528 Errata Sheet (if applicable)
ORDERING INFORMATION
PART DS26528DK DESCRIPTION DS26528 Demo Kit Daughter Card (with included DK101 Motherboard)
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REV: 021405
DS26528DK
COMPONENT LIST
DESIGNATION
C1-C5, C7, C8, C9, C20, C21, C29-C32, C35, C40, C41, C43, C49, C50, C59, C60 C6, C10-C18, C24, C33, C36-C39, C42, C44-C48 C19, C22, C23, C25-C28, C34, C61, C62 C51-C58 C63-C70 D1 DS1 DS2-DS18 J1 J2-J9 J10-J25 J26, J27 J28, J29 JP1 JP2, JP3, JP5-JP8 JP4 R1-R32 R33 R34, R35, R39-R54 R36, R38, R55 R37 R56-R71 R72-R79 SW1-SW8 T1, T2 U1 U2 U3 U4
QTY
22
DESCRIPTION
1mF 10%, 16V ceramic capacitors (1206)
SUPPLIER
Panasonic
PART
ECJ-3YB1C105K
22
0.1mF 20%, 16V X7R ceramic capacitors (0603)
Arrow
0603YC104MAT2
10 8 8 1 1 17 1 8 16 2 2 1 6 1 32 1 18 3 1 16 8 8 2 1 1 1 1
10mF 20%, 10V ceramic capacitors (1206) 0.1mF 10%, 25V ceramic capacitors (1206) 560pF 5%, 50V ceramic capacitors (1206) L_DIODE 1A, 50V general-purpose silicon L_LED, GREEN, SMD LED, RED, SMD L_TERMINAL strip, 10-pin, dual-row, vertical 22-pin headers, dual row, vertical L_ 5-pin, 75W vertical BNC connectors Right-angle RJ45 8-pin, 4-port jack 50-pin, dual-row, vertical SMD sockets 12-pin, dual-row, vertical connector 100-mil, 2 pos jumper Not populated 12-pin, dual row, vertical connector Not populated 0W 5%, 1/8W resistors (1206) L_RES 330W 5%, 1/16W resistors (0603) 330W 5%, 1/10W resistors (0805) 10kW 5%, 1/16W resistors (0603) 30W 5%, 1/10W resistor (0805) 61.9W 1%, 1/8W resistors (1206) L_RES 51.1W 1%, 1/10W resistors (0805) (ok to substitute for 5%) 6-pin, DPDT, through-hole slide switches XFMR, XMIT/RCV, 1 to 2 and 1 to 1, SMT 32-pin 8-Pin mMAX/SO 2.5V or Adj 1Mb flash-based config mem Xilinx Spartan 2.5V FPGA, 256-pin BGA 256-pin BGA octal transceiver (0C to +70C)
Panasonic Panasonic Digi-Key General Semiconductor Panasonic Panasonic Samtec Samtec Cambridge Molex Samtec Digi-Key Labstock Digi-Key Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Tyco Pulse Engineering Maxim Xilinx Xilinx Dallas Semiconductor
ECJ-3YB1A106M ECJ-3VB1E104K 478-1489-2-ND 1N4001 LN1351C LN1251C TSW-105-07-T-D HDR-TSW-111-14-T-D CP-BNCPC-004 43223-8140 TFM-125-02-S-D-LC S2012-06-ND Not populated S2012-06-ND ERJ-8GEYJ0R00V ERJ-3GEYJ331V ERJ-6GEYJ331V ERJ-3GEYJ103V ERJ-6GEYJ300V ERJ-8ENF61R9V ERJ-6ENF51R1V SSA22 TX1475 MAX1792EUA25 XCF01SV020C XC2S50-5FG256C DS26528
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DS26528DK
BOARD FLOORPLAN
TEST POINTS TSYSCLK, TSSYNC, RSYSCLK, BPCLK, REFCLK, MCLK INT LED
CPU INTERFACE CPU INTERFACE
QUAD-PORT TRANSFORM
TEST POINTS: RCLKn, TCLKn RSERn, TSERn RSYNCn, TSYNCn RCHBKn, TCHBKn RSIGn, TSIGn RMn (n = PORT 5 TO 8)
RLF 5 TO 8 LEDs RLOS 5 TO 8 LEDs
BNC PORT 8
BNC PORT 6 BNC PORT 5 BNC PORT 4
FPGA STATUS LED
FPGA
PCM BUS TEST POINTS
DS26528
FPGA CONFIG PROM JTAG
TEST POINTS: RCLKn, TCLKn RSERn, TSERn RSYNCn, TSYNCn RCHBKn, TCHBKn RSIGn, TSIGn RMn (n = PORT 1 TO 4)
QUAD-PORT TRANSFORM
BNC PORT 2 BNC PORT 1
RLOS 1 TO 4 LEDs RLF 1 TO 4 LEDs
PC BOARD ERRATA
* The mode pins of the FPGA were incorrectly connected, which affects FPGA configuration. The hardware modifications to correct this are not ideal, as the FPGA is in a race condition during power-up. The FPGA requires a fast slew rate on VCC during power-up. After power-up the LED DS1 will light green if FPGA configuration is successful. If the DS1 LED does not light green, cycle power by removing and reattaching the VCC banana plug. The removal/reattach of the VCC banana plug results in a faster slew rate on VCC than simply cycling the power supply.
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RJ 45 x 4
2.5V FPGA SUPPLY
BNC PORT 3
RJ 45 x 4
BNC PORT 7
DS26528DK
BASIC OPERATION
This design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/DS26528DK QuickView data sheet for these files.
HARDWARE CONFIGURATION
Using the DK101 Processor Board:
* * * * Connect the daughter card to the DK101 processor board. Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is unused. Additionally, the "TIM 5V supply" headers are unused.) All processor board DIP switch settings should be in the ON position with exception for the Flash programming switch, which should be OFF. From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs (R) ChipView (R) ChipView.
Using the DK2000 Processor Board:
* * * Connect the daughter card to the DK2000 processor board. Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply may be connected to connector J2. From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs (R) ChipView (R) ChipView.
General:
* * Upon power-up the RLOS LEDs (red) will be lit, the INT LED (red) will not be lit, and the FPGA Status LED (DS1 green) will be lit. (See the PC Board Errata section note regarding FPGA power-up configuration on page 3). When using BNC network connections, slide SW1-SW8 such that the BNC shell is grounded (indicated by the PC board silkscreen). When using RJ45 network connections, slide SW1-SW8 such that the BNC shell is not grounded (indicated by the PC board silkscreen).
QUICK SETUP (REGISTER VIEW)
* * * * The PC will load ChipView offering a choice among DEMO MODE, REGISTER VIEW, and TERMINAL MODE. Select REGISTER VIEW. The program will request a definition file. Navigate to the .def files in the T1 or E1 folder, then select the _DS26528DK01A0_FPGA.def. Note: Through the "links" section this will also load the DS26528 global def file along with eight LIU def files and eight framer def files. The Register View Screen will appear, showing the register names, acronyms, and values for the DS26528. Predefined register settings for several functions are available as initialization files. * .ini files are loaded by selecting the menu File(R)Reg Ini File(R)Load Ini File. * Load the .ini file E1_75ohmLiu_ impMatchOn.ini. * After loading the .ini file, the following may be observed: * The RLOS LEDs extinguishes upon external loopback. * The DS26528 is in E1 mode with impedance match on and begins transmitting AIS.
Miscellaneous:
* * Clock frequencies, port-to-port connection, and certain pin bias levels are provided by a register-mapped FPGA that is on the DS26528 daughter card. The definition file for this FPGA is named DS26528DC_FPGA.def. The FPGA register map definitions are located on page 6. A drop-down menu on the right of the screen allows for switching between definition files. All files referenced above are available for download as described in the section marked "BASIC OPERATION." 4 of 36
*
DS26528DK
ADDRESS MAP
The DK101 daughter card address space begins at 0x81000000. The DK2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 All offsets given in the following table(s) are relative to the beginning of the daughter card address space (shown above).
Table 1. Daughter Card Address Map
OFFSET 0X0000 to 0X0087 0X1000 to 0X10EF 0X10F0 to 0X10FF 0X1100 to 0X11EF 0X11F0 to 0X11FF 0X1200 to 0X1FFF 0X2000 to 0X20FF 0X2100 to 0X217F 0X2180 to 0X2FFF DEVICE FPGA DS26528 DS26528 DS26528 DS26528 DS26528 DS26528 DS26528 DS26528 DESCRIPTION Board identification and clock/signal routing DS26528 Framer 1 Rx registers DS26528 Global registers DS26528 Framer 1 Tx registers DS26528 reserved registers DS26528 Framer 2 to 8 registers DS26528 LIU 1 to 8 registers DS26528 BERT 1 to 8 registers DS26528 reserved registers
Registers in the FPGA can be easily modified using the ChipView host-based user interface software along with the definition file named "DS26528DC_FPGA.def."
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DS26528DK
FPGA Register Map
Table 2. FPGA Register Map
OFFSET 0X0000 0X0002 0X0003 0X0004 0X0005 0X0006 0X0007 0X0010 0X0011 0X0012 0X0013 0X0014 0X0024 0X0034 0X0044 0X0054 0X0064 0X0074 0X0084 0X0015 0X0025 0X0035 0X0045 0X0055 0X0065 0X0075 0X0085 0X0016 0X0026 0X0036 0X0046 0X0056 0X0066 0X0076 0X0086 0X0017 0X0027 0X0037 0X0047 0X0057 0X0067 0X0077 0X0087 0X0018 0X0019 0X001A REGISTER NAME BID XBIDH XBIDM XBIDL BREV AREV PREV PINSET CSR SYSCLK_TR SYNCTSS TYPE Read only Read only Read only Read only Read only Read only Read only Control Control Control Control DESCRIPTION Board ID High Nibble Extended Board ID Middle Nibble Extended Board ID Low Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision DS26528 Configuration Pin Settings DS26528 MCLK and REFCLKIO Source DS26528 Tx and Rx SYSCLK Source DS26528 TSSYNC Source
TCSRn (n = 8 to 1)
Control
DS26528 TCLK Source, Ports 8-1
TSYNCSn (n = 8 to 1)
Control
DS26528 TSYNC Source, Ports 8-1
RSYNCSRn (n = 8 to 1)
Control
DS26528 RSYNC Source Select, Ports 8-1
TSERSRn (n = 8 to 1)
Control
DS26528 TSER Source, Ports 8-1
PRSER PSYNC PCLK
Control Control Control
PCM RSER Source PCM RSYNC/TSYNC Source PCM RCLK/TCLK Source 6 of 36
DS26528DK
ID REGISTERS
BID: BOARD ID (Offset=0X0000) BID is read only with a value of 0xD. XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset=0X0002) XBIDH is read only with a value of 0x0. XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset=0X0003) XBIDM is read only with a value of 0x1. XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset=0X0004) XBIDL is read only with a value of 0x6. BREV: BOARD FAB REVISION (Offset=0X0005) BREV is read only and displays the current fab revision. AREV: BOARD ASSEMBLY REVISION (Offset=0X0006) AREV is read only and displays the current assembly revision. PREV: PLD REVISION (Offset=0X0007) PREV is read only and displays the current PLD firmware revision.
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DS26528DK
CONTROL REGISTERS
Register Name: PINSET Register Description: DS26528 Configuration Pin Settings Register Offset: 0x0010
Bit # Name Default 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 TXEN 1 2 SCANMO 0 1 SCANEN 0 0 DIGIOEN 1
Bit 3: DS26528 TXEN PIN
0 = Drive DS26528 TX ENABLE pin Low (Tri-state TTIP and TRING) 1 = Drive DS26528 TX ENABLE pin High (Normal operation, drive TTIP and TRING with data)
Bit 2: DS26528 SCANMO PIN
0 = Drive DS26528 SCAN MODE pin Low (Normal operation) 1 = Drive DS26528 SCAN MODE pin High
Bit 1: DS26528 SCANEN PIN
0 = Drive DS26528 SCAN ENABLE pin Low (Normal operation) 1 = Drive DS26528 SCAN ENABLE pin High
Bit 0: DS26528 DIGIOEN PIN
0 = Drive DS26528 DIGIO ENABLE pin Low (Tri-state all DS26528 pins, if JTRST is low) 1 = Drive DS26528 DIGIO ENABLE pin High (Normal operation)
Register Name: CSR Register Description: DS26528 MCLK and REFCLKIO Source Register Offset: 0x0011
Bit # Name Default 7 RCSRC1 1 6 RCSRC0 1 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 MSRC1 0 0 MSRC0 1
Bits 7 and 6: DS26528 REFCLKIO Source (RCSRC[1:0])
REFCLKIO Connection is defined in Table 3.
Table 3. REFCLKIO Source Definition
RCSRC1, RCSRC0 00 01 1x REFCLKIO CONNECTION Drive REFCLKIO with the 1.544MHz clock Drive REFCLKIO with the 2.048MHz clock Tri-state REFCLKIO
Bits 1 and 0: DS26528 MCLK Source (MSRC[1:0]
MCLK Connection is defined in Table 4.
Table 4. MCLK Source Definition
MSRC1, MSCR0 00 01 1x MCLK CONNECTION Drive MCLK with the 1.544MHz clock Drive MCLK with the 2.048MHz clock Tri-state MCLK 8 of 36
DS26528DK
Register Name: SYSCLK_TR Register Description: DS26528 TSYSCLK and RSYSCLK Source Register Offset: 0x0012
Bit # Name Default 7 RS1 0 6 RS0 1 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 TS1 0 0 TS0 1
Bits 7 and 6: DS26528 Port 4 RSYSCLK Source (RS1, RS0)
The source for RSYSCLK 4 is defined as shown in Table 5.
Table 5. RSYSCLK Source Definition
RS1, RS0 00 01 10 11 RSYSCLK CONNECTION Drive RSYSCLK with the 1.544MHz clock Drive RSYSCLK with the 2.048MHz clock Drive RSYSCLK with 8.192MHz clock Drive RSYSCLK with DS26528 port BPCLK
Bits 1 and 0: DS26528 Port 1 TSYSCLK Source (TS1, TS0)
The source for TSYSCLK is defined as shown in Table 6.
Table 6. TSYSCLK Source Definition
TS1, TS0 00 01 10 11 TSYSCLK CONNECTION Drive TSYSCLK with the 1.544MHz clock Drive TSYSCLK with the 2.048MHz clock Drive TSYSCLK with 8.192MHz clock Drive TSYSCLK with DS26528 port BPCLK
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DS26528DK
Register Name: SYNCTSS Register Description: DS26528 TSSYNC Source Register Offset: 0x0013
Bit # Name Default 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 TSRC3 0 2 TSRC2 0 1 TSRC1 0 0 TSRC0 0
Bit 3 to 0: DS26528 TSSYNC Source Select (TSRC[3:0])
The source for TSSYNC is defined below. TSRC3-TSRC0 0000 0001 0010 0011 0100 0101 0110 0111 1000 TSSYNC SOURCE DEFINITION Not using transmit-side elastic store, tri-state FPGA pin connected to TSSYNC (weak pulldown) Drive TSSYNC with RSYNC 1 Drive TSSYNC with RSYNC 2 Drive TSSYNC with RSYNC 3 Drive TSSYNC with RSYNC 4 Drive TSSYNC with RSYNC 5 Drive TSSYNC with RSYNC 6 Drive TSSYNC with RSYNC 7 Drive TSSYNC with RSYNC 8
Note: When driving TSSYNC with RSYNCx, the corresponding DS26528 port should be configured such that RSYNCx is an output (RIOCR.2 = 0).
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DS26528DK
Register Name: TCSRn (n = 8 to 1) Register Description: DS26528 TCLK Source Ports 8-1 Register Offset: 0x0014, 0x0024, 0x0034, 0x0044, 0x0054, 0x0064, 0x0074, 0x0084,
Bit # Name Default 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 TDS3
See note
2 TDS2
See note
1 TDS1
See note
0 TDS0
See note
Bits 3 to 0: DS26528 Port 1 TCLK Source (TDS[3:0])
TDS3-TDS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 TCLKx SOURCE DEFINITION Tri-state TCLKx Drive TCLKx with RCLK1 Drive TCLKx with RCLK2 Drive TCLKx with RCLK3 Drive TCLKx with RCLK4 Drive TCLKx with RCLK5 Drive TCLKx with RCLK6 Drive TCLKx with RCLK7 Drive TCLKx with RCLK8 Drive TCLKx with the 1.544MHz clock Drive TCLKx with the 2.048MHz clock
Note: Initial values are such that TCLK1RCLK1, TCLK2RCLK2, TCLK3RCLK3, TCLK4RCLK4, TCLK5RCLK5, TCLK6RCLK6, TCLK7RCLK7, TCLK8RCLK8, which corresponds to address 0x14 = 0b0001, address 0x24 = 0b0010, address 0x34 = 0b0011, address 0x44 = 0b0100, address 0x54 = 0b0101, address 0x64 = 0b0110, address 0x74 = 0b0111 and address 0x84 = 0b1000.
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DS26528DK
Register Name: TSYNCSn (n = 8 to 1) Register Description: DS26528 TSYNC Source Ports 8-1 Register Offset: 0x0015, 0x0025, 0x0035, 0x0045, 0x0055, 0x0065, 0x0075, 0x0085
Bit # Name Default 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 TSRC3 0 2 TSRC2 0 1 TSRC1 0 0 TSRC0 0
Bits 3 to 0: DS26528 Port 1 TSYNC Source (TSRC[3:0])
TSRC3-TSRC 0000 0001 0010 0011 0100 0101 0110 0111 1000 TSYNCx SOURCE DEFINITION Tri-state TSYNCx Drive TSYNCx with RSYNC1 Drive TSYNCx with RSYNC2 Drive TSYNCx with RSYNC3 Drive TSYNCx with RSYNC4 Drive TSYNCx with RSYNC5 Drive TSYNCx with RSYNC6 Drive TSYNCx with RSYNC7 Drive TSYNCx with RSYNC8
Note: When driving TSYNCx with RSYNCx, the corresponding DS26528 port should be configured such that TSYNCx is an input (TIOCR.2 = 0) and RSYNCx is an output (RIOCR.2 = 0).
Register Name: RSYNCSRn (n = 8 to 1) Register Description: DS26528 RSYNC Source Select, Ports 8-1 Register Offset: 0x0016, 0x0026, 0x0036, 0x0046, 0x0056, 0x0066, 0x0076, 0x0086
Bit # Name Default 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 RIO3 0 2 RIO2 0 1 RIO1 0 0 RIO0 0
Bits 3 to 0: DS26528 Port 1 RSYNC Source (RIO[3:0])
RIO3-RIO0 0000 0001 0010 0011 0100 0101 0110 0111 1000 RSYNCx SOURCE DEFINITION Tri-state RSYNCx Drive RSYNCx with RSYNC1 Drive RSYNCx with RSYNC2 Drive RSYNCx with RSYNC3 Drive RSYNCx with RSYNC4 Drive RSYNCx with RSYNC5 Drive RSYNCx with RSYNC6 Drive RSYNCx with RSYNC7 Drive RSYNCx with RSYNC8
Note: When driving RSYNCy with RSYNCx, the corresponding DS26528 port should be configured such that RSYNCx is an output (RIOCR.2 = 0) and RSYNCy is an input (RIOCR.2 = 1).
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DS26528DK
Register Name: TSERSRn (n = 8 to 1) Register Description: DS26528 TSER Source, Ports 8-1 Register Offset: 0x0017, 0x0027, 0x0037, 0x0047, 0x0057, 0x0067,0x0077, 0x0087
Bit # Name Default 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 TS3
See note
2 TS2
See note
1 TS1
See note
0 TS0
See note
Bits 3 to 0: DS26528 Port 1 TSER Source (TSRC[3:0])
TS3-TS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 TSERx SOURCE DEFINITION Tri-state TSERx Drive TSERx with RSER1 Drive TSERx with RSER2 Drive TSERx with RSER3 Drive TSERx with RSER4 Drive TSERx with RSER5 Drive TSERx with RSER6 Drive TSERx with RSER7 Drive TSERx with RSER8 Drive TSERx with data from PCM bus
Note: Initial values are such that TSER1RSER1, TSER2RSER2, TSER3RSER3, TSER4RSER4, TSER5RSER5, TSER6RSER6, TSER7RSER7, TSER8RSER8, which corresponds to address 0x17 = 0b0001, address 0x27 = 0b0010, address 0x37 = 0b0011, address 0x47 = 0b0100, address 0x57 = 0b0101, address 0x67 = 0b0110, address 0x77 = 0b0111 and address 0x87 = 0b1000.
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DS26528DK
Register Name: PRSER Register Description: PCM RSER Source Register Offset: 0x0018
Bit # Name Default 7 R8EN 0 6 R7EN 0 5 R6EN 0 4 R5EN 0 3 R4EN 0 2 R3EN 0 1 R2EN 0 0 R1EN 0
Note: The PRSER register is for use with the DK2000 only.
Bit 7: PCM RSER Source (R8EN)
0 = Do not drive DS26528 Port 8 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 8 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 6: PCM RSER Source (R7EN)
0 = Do not drive DS26528 Port 7 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 7 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 5: PCM RSER Source (R6EN)
0 = Do not drive DS26528 Port 6 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 6 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 4: PCM RSER Source (R5EN)
0 = Do not drive DS26528 Port 5 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 5 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 3: DS26528 PCM RSER Source (R4EN)
0 = Do not drive DS26528 Port 4 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 4 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 2: PCM RSER Source (R3EN)
0 = Do not drive DS26528 Port 3 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 3 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 1: PCM RSER Source (R2EN)
0 = Do not drive DS26528 Port 2 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 2 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 0: PCM RSER Source (R1EN)
0 = Do not drive DS26528 Port 1 RSER onto PCM_RSER 1 = Logically OR DS26528 Port 1 RSER with selected other RSER pins and drive onto PCM_RSER
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DS26528DK
Register Name: PSYNC Register Description: PCM RSYNC/TSYNC Source Register Offset: 0x0019
Bit # Name Default 7 TSR3 0 6 TSR2 0 5 TSR1 0 4 TSR0 0 3 RSR3 0 2 RSR2 0 1 RSR1 0 0 RSR0 0
Note: PSYNC register is for use with the DK2000 only.
Bits 7 to 4: PCM_TSYNC Source (TSR[3:0])
TSR3-TSR0 0000 0001 0010 0011 0100 0101 0110 0111 1000 PCM_TSYNC SOURCE Tri-state PCM_TSYNC PCM_TSYNC is driven by DS26528 port 1 TSYNC PCM_TSYNC is driven by DS26528 port 2 TSYNC PCM_TSYNC is driven by DS26528 port 3 TSYNC PCM_TSYNC is driven by DS26528 port 4 TSYNC PCM_TSYNC is driven by DS26528 port 5 TSYNC PCM_TSYNC is driven by DS26528 port 6 TSYNC PCM_TSYNC is driven by DS26528 port 7 TSYNC PCM_TSYNC is driven by DS26528 port 8 TSYNC
Bits 3 to 0: PCM_RSYNC Source (RSR[3:0])
RSR3-RSR0 0000 0001 0010 0011 0100 0101 0110 0111 1000 PCM_RSYNC SOURCE Tri-state PCM_RSYNC PCM_RSYNC is driven by DS26528 port 1 RSYNC PCM_RSYNC is driven by DS26528 port 2 RSYNC PCM_RSYNC is driven by DS26528 port 3 RSYNC PCM_RSYNC is driven by DS26528 port 4 RSYNC PCM_RSYNC is driven by DS26528 port 5 RSYNC PCM_RSYNC is driven by DS26528 port 6 RSYNC PCM_RSYNC is driven by DS26528 port 7 RSYNC PCM_RSYNC is driven by DS26528 port 8 RSYNC
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DS26528DK
Register Name: PCLK Register Description: PCM RCLK/TCLK Source Register Offset: 0x001A
Bit # Name Default 7 TSR3 0 6 TSR2 0 5 TSR1 0 4 TSR0 0 3 RSR3 0 2 RSR2 0 1 RSR1 0 0 RSR0 0
Note: PCLK register is for use with the DK2000 only.
Bits 7 to 4: PCM_TCLK Source (TSR[3:0])
TSR3--TSR0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 PCM_TCLK SOURCE Tri-state PCM_TCLK pin at FPGA PCM_TCLK is driven by source used for DS26528 port 1 TCLK PCM_TCLK is driven by source used for DS26528 port 2 TCLK PCM_TCLK is driven by source used for DS26528 port 3 TCLK PCM_TCLK is driven by source used for DS26528 port 4 TCLK PCM_TCLK is driven by source used for DS26528 port 5 TCLK PCM_TCLK is driven by source used for DS26528 port 6 TCLK PCM_TCLK is driven by source used for DS26528 port 7 TCLK PCM_TCLK is driven by source used for DS26528 port 8 TCLK PCM_TCLK is driven by DS26528 BPCLK
Bits 3 to 0: PCM_RCLK Source (RSR[3:0])
RSR3-RSR0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 PCM_RCLK SOURCE Tri-state PCM_RCLK pin at FPGA PCM_RCLK is driven by DS26528 port 1 RCLK PCM_RCLK is driven by DS26528 port 2 RCLK PCM_RCLK is driven by DS26528 port 3 RCLK PCM_RCLK is driven by DS26528 port 4 RCLK PCM_RCLK is driven by DS26528 port 5 RCLK PCM_RCLK is driven by DS26528 port 6 RCLK PCM_RCLK is driven by DS26528 port 7 RCLK PCM_RCLK is driven by DS26528 port 8 RCLK PCM_RCLK is driven by DS26528 BPCLK
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DS26528DK
FPGA CONTROL EXAMPLES
Scenario #1: DS26528 to/from DK2000 DS26528 TSER TCLK BPCLK TSYNC RSER RCLK BPCLK RSYNC XO DK2000 PCM_TXD PCM_TCLK PCM_TSYNC PCM_RXD PCM_RCLK PCM_RSYNC
Table 7. FPGA Configuration for Scenario #1 (Port 1, T1 Mode)
REGISTER NAME CSR TCSR1 SYSCLK_TR TSYNCS1 SYNCTSS RSYNCSRn TSERSR1 PRSER PSYNC PCLK SETTING 0X01 0X09 0X00 0X00 0X01 0X00 0X09 0X01 0X11 0X99 COMMENT Drive DS26528 MCLK with 2.048MHz Drive TCLK with 1.544MHz Drive TSYSCLK and RSYSCLK with 1.544MHz Tri-state FPGA driver pin for DS26528 TSYNC1 Drive TSSYNC with RSYNC1 Tri-state FPGA driver pin for DS26528 RSYNC Drive DS26528 TSER1 with data from PCM bus Drive DS26528 RSER1 onto PCM bus PCM RSYNC and PCM TSYNC are provided by DS26528 port 1 RSYNC and TSYNC (respectively) PCM RCLK and TCLK are driven by port 1 BPCLK
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DS26528DK Scenario #2: External Remote Loopback (full bandwidth, not just payload) DS26528 TSER TCLK BPCLK TSYNC RSER RCLK BPCLK RSYNC
Table 8. FPGA Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER NAME CSR TCSR1 SYSCLK_TR TSYNCS1 SYNCTSS RSYNCSRN TSERSR1 PRSER PSYNC PCLK SETTING 0X01 0X01 0X00 0X01 0X01 0X00 0X01 NA NA NA COMMENT Drive DS26528 MCLK with 2.048MHz Drive TCLK1 with RCLK1 Drive TSYSCLK with 1.544MHz Drive TSYNC1 with RSYNC1 Drive TSSYNC with RSYNC1 Tri-state FPGA driver pin for DS26528 RSYNC Drive DS26528 TSER1 with data from RSER1 Unused Unused Unused
Table 9. DS26528 Partial Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER NAME RIOCR TIOCR TESCR RESCR TCR3 SETTING RSIO = 0 TSIO = 0 TESE = 0 RESE = 0 TCSS1 = 0 TCSS2 = 0 RSYNC is an output TSYNC is an input Bypass Rx and Tx elastic stores TCLK is driven by TCLK pin COMMENT
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DS26528DK
DS26528 INFORMATION
For more information about the DS26528, consult the DS26528 data sheet available on our website at www.maxim-ic.com/DS26528. Software downloads are also available for this design kit.
DS26528DK INFORMATION
For more information about the DS26528DK, including software downloads, consult the DS26528DK data sheet available on our website at www.maxim-ic.com/DS26528DK.
TECHNICAL SUPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS26528DK schematics are featured in the following pages.
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
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